Test and Measurement Technical Data
dS-NET VSIO Adaptor Pinouts
GENERATOR OUTPUT
| D-sub pin (15way male) | Signal | Direction | Description |
| 1 | GEN_DATA0 | Output | Generator Data Channel 0 |
| 9 | GND | - | Ground |
| 2 | GEN_DATA1 | Output | Generator Data Channel 1 |
| 10 | GND | - | Ground |
| 3 | GEN_DATA2 | Output | Generator Data Channel 2 |
| 11 | GND | - | Ground |
| 4 | GEN_DATA3 | Output | Generator Data Channel 3 |
| 12 | GND | - | Ground |
| 5 | GEN_LRCK | I/O | Generator Frame Clock |
| 13 | GND | - | Ground |
| 6 | GEN_SCK | I/O | Generator Bit Clock |
| 14 | GND | - | Ground |
| 7 | GEN_MCK | I/O | Generator Master Clock |
| 15 | GND | - | Ground |
| 8 | NC | passive | No Connection |
ANALYZER INPUT
| D-sub pin (15way male) | Signal | Direction | Description |
| 1 | ANA_DATA0 | Input | Analyzer Data Channel 0 |
| 9 | GND | - | Ground |
| 2 | ANA_DATA1 | Input | Analyzer Data Channel 1 |
| 10 | GND | - | Ground |
| 3 | ANA_DATA2 | Input | Analyzer Data Channel 2 |
| 11 | GND | - | Ground |
| 4 | ANA_DATA3 | Input | Analyzer Data Channel 3 |
| 12 | GND | - | Ground |
| 5 | ANA_LRCK | I/O | Analyzer Frame Clock |
| 13 | GND | - | Ground |
| 6 | ANA_SCK | I/O | Analyzer Bit Clock |
| 14 | GND | - | Ground |
| 7 | ANA_MCK | I/O | Analyzer Master Clock |
| 15 | GND | - | Ground |
| 8 | NC | passive | No Connection |
CONTROL INTERFACE
| D-sub pin (9 way male) | Signal | Direction | Description |
| 1 | CTRL_CK | I/O | SPI Clock / I2C SCL |
| 6 | GND | - | Ground |
| 2 | CDAT-IN | I/O | SPI Data In / I2C SDA |
| 7 | GND | - | Ground |
| 3 | CDAT-OUT | Output | SPI Data Out |
| 8 | GND | - | Ground |
| 4 | CTRL_CS | Output | SPI Chip Select |
| 9 | GND | - | Ground |
| 5 | NC | passive | No Connection |
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